The Edinburgh Simple Processor is a simulation model designed to show how the main component of a computer, the processor, works. It can be downloaded as an APPLET and either used directly as a demonstration or used for assembly code programming exercises. Please note that to use the applet, you need to have JavaHASE JDK 1.3 (or higher) enabled in your browser (the JavaHASE page gives more details).
The picture below shows how the processor appears in the applet:
An important feature of any processor is its instruction set. EPS has an instruction set similar to that of most modern microprocessors, i.e. it contains simple load/store and register-register arithmetic operations. In real processors these instructions are held as binary numbers and are largely unintelligible to humans. ESP holds its programs in readable, assembly code format. When the applet is downloaded, the Instruction Memory contains an assembly code program which uses add, shift and test & branch instructions to multiply two numbers together. The two numbers to be multiplied are held in words 0 and 1 of the Data Memory. At the end of the program, the result is written into word 2. The program and data can be viewed in the applet by right clicking the mouse when the pointer is over the appropriate Memory box and then clicking on the pop-up parameters menu box. More detail about the program can be found below.
The other components in the processor are a set of 16 Registers (which can also be viewed by right clicking on the box), an arithmetic/logic unit (ALU), a Program Counter (PC), a Control Unit and two Buses used to connect the various units together. The processor is controlled by the Control Unit and driven by a clock. The clock has a two-phase cycle. In the first phase of a clock cycle, any unit which is active executes its internal actions. For example, if the Data Memory has received a command from the Control Unit instructing it to read a data value, it will do this in the first phase of the clock and will send the value to BUS1 in the second phase. The Data Memory has a built-in Memory Address Register (MAR) and a Memory Buffer Register (MBR). When a data item is to be written into the Data Memory, the address is sent via BUS2 to MAR and the data via BUS1 to MBR. When a data item is to be read, the address is sent to MAR and the value appears in MBR.
The Program Counter unit contains the Program Counter register together with an adder (ADD) and a multiplexer (MPX). PC has two outputs, one connected back to the adder and one to the memory. The other input to the adder comes from the multiplexer which can be set to accept an input of +1 or a value taken from BUS2. Whenever PC is updated with a new value, this value is sent as an address to the Instruction Memory, causing it to read the instruction at that address.
Once the Instruction Memory has read the the instruction, it sends it to the Control Unit. The Control Unit loads the instruction into its Instruction Register (IR) and proceeds to send signals (not shown in the applet) to the other units, causing the instruction to be executed. To add two numbers together, for example, the Control Unit sends a command to the Registers Unit telling it to read the values in the two source registers and send them to the buses. The buses send any values sent to them to all of their outputs but the Control Unit decides which unit should actually uses them, in this case the ALU. The ALU adds the two values together and sends the result back to the Registers. The Registers Unit is then told to write the value into the destination register and, at the same time, the Program Counter is told to add +1 to its current value, causing the next instruction to be fetched from the Instruction Memory.
The Registers unit contains 16 registers (R00 - R15), with R00 being permanently set to 0. It receives input values from the ALU and has two outputs, one connected to BUS1 and the other to BUS2. In an instruction such as ADD RD RS1 RS2, the value in register RS1 is sent to BUS1 and that in RS2 to BUS2.
The ALU has two data inputs, from BUS1 and BUS2, and two outputs, one connected to the Registers Unit and one to BUS2. Whenever the Control Unit sends a command to the ALU, it includes the appropriate function code taken from the instruction in IR. There are two condition code bits: CC0 is set = 0 if the ALU result = 0; CC1 is set = 1 if the ALU result < 0. The ALU can execute the following functions:
Add Subtract AND OR XOR Shift Left Logical Shift Right Logical Shift Right Arithmetic
The CC values are used by the Control Unit to determine the outcome of a branch. The two branches are BEQZ (branch if zero) and BNEG (branch if negative). If the condition is satisfied, the Literal value in the instruction is added to PC, otherwise PC is simply incremented as for other instructions. The full set of instructions is shown below:
ESP Instruction Set
Instruction Action JUMP Literal PC = Literal JREG RS PC = RS (i.e. the value in RS) BEQZ Literal If CC0 = 0, PC = PC + Literal, else PC = PC + 1 BNEG Literal If CC1 = 1, PC = PC + Literal, else PC = PC + 1 LD RD Address RD = Memory[Address] LDL RD Literal RD = Literal LDX RD Address(RS) RD = Memory[Address+RS] ST Address RS Memory[Address] = RS STX Address(RS2) RS1 Memory[Address+RS2] = RS1 ADD RD RS1 RS2 RD = RS1 + RS2 ADDL RD RS1 Literal RD = RS1 + Literal SUB RD RS1 RS2 RD = RS1 - RS2 SUBL RD RS1 Literal RD = RS1 - Literal AND RD RS1 RS2 RD = RS1 & RS2 ANDL RD RS1 Literal RD = RS1 & Literal OR RD RS1 RS2 RD = RS1 | RS2 ORL RD RS1 Literal RD = RS1 | Literal XOR RD RS1 RS2 RD = RS1 ^ RS2 XORL RD RS1 Literal RD = RS1 ^ Literal SLL RD RS1 RS2 RD = RS1 << RS2 (Shift Left Logical) SLLL RD RS1 Literal RD = RS1 << Literal SRL RD RS1 RS2 RD = RS1 >> RS2 (Shift Right Logical) SRLL RD RS1 Literal RD = RS1 >> Literal SRA RD RS1 RS2 RD = RS1 >> RS2 (Shift Right Arithmetic) SRAL RD RS1 Literal RD = RS1 >> Literal STOP Stops the simulation
Demonstration ProgramThe assembly code program in the applet's Instruction Memory uses add, shift and test & branch instructions to multiply two numbers together using binary arithmetic. The program involves a simple loop of instructions which is repeated as many time as necessary, up to a maximum of 16 times. The program first initialises two register values (in R1 and R2) to 0 and 16. R1 counts the number of loop executions and R2 contains the running total which will eventually become the result. The multiplicand is read from memory and copied into R3 while the multipier is copied into R4. Each time round the loop, the least significant bit of R4 is tested (by ANDing it with 1 and copying it into R5). If it is 1, the multiplicand is added to the running total. The multiplicand is multiplied by 2 (by shifting it left by one place) each time the loop is executed and the multiplier is shifted right so that the next digit can be tested. If all the bits equal to 1 in the multiplier have been used (i.e. its value becomes zero) the program branches to the instruction which writes the result in R2 to memory location 2. If the multiplier is not zero, the program decrements R1. If R1 is zero, the program branches to the instruction which writes the result to memory (this means that the program will not work properly with multiplier values which are greater than 65,536 or are negative). If R1 is non-zero, the program jumps back to the start of the loop (i.e. the ANDL instruction).
The instructions in the program are as follows:
ADDL R1 R0 16 // Sets R1 = 16 ADDL R2 R0 0 // Sets R2 = 0 LD R3 0 // Loads the value in memory location 0 into R3 LD R4 1 // Loads the value in memory location 1 into R4 ANDL R5 R4 1 // ANDs the value in R4 with 1 and copies the result into R5 BEQZ 2 // Branches to SLLL instruction if R4&1 = 0 ADD R2 R2 R3 // Adds the value in R3 to the value in R2 SLLL R3 R3 1 // Shifts the value in R3 left by 1 SRLL R4 R4 1 // Shifts the value in R4 right by 1 BEQZ 4 // Branches to ST instruction if value in R4 = 0 SUBL R1 R1 1 // Decrements R1 BEQZ 2 // Branches to ST instruction if value in R1 = 0 JUMP 4 // Jumps to instruction 4 (ANDL) ST 2 R2 // Stores the value in R2 in Data Memory location 2 STOP // Stops the simulation
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