In a bus-based multiprocessor system, cache coherence can be ensured using a snoopy protocol in which each processor's cache monitors the traffic on the bus and takes appropriate action when it sees a write request being sent to memory for a variable at an address matching one that it holds. This website contains a number of models demonstrating different types of snoopy protocol:Return to Computer Architecture Simulation Models
Instructions on how to use HASE models can be found at Downloading, Installing and Using HASE.
- Write Through / Write Invalidate protocol, for which the model files can be downloaded as a tar file from wti-cache.tar.gz or as a zip file from wti-cache.zip
- Write Through / Write Update protocol, for which the model files can be downloaded as a tar file from wtu-cache.tar.gz or as a zip file from wtu-cache.zip
- Copyback / Write Invalidate protocol, for which the model files can be downloaded as a tar file from cbi-cache.tar.gz or as a zip file from cbi-cache.zip
