The DLX is an `average' register-register load/store architecture designed by Hennesssy and Patterson [1]. A full instruction set manual has also been produced for it [2]. The DLX has been used extensively in teaching and numerous DLX simulators have been developed (e.g. [3] [4] [5]).
The figure shows a typical `implementation' of a simple DLX pipelined architecture. The Integer Unit is used for both data and address arithmetic, so load/store instructions are processed by the Integer Unit before being sent to the Memory Access Unit and thence to Memory. The Integer Unit also executes the additions required for integer test and relative branch instructions, so the Memory Access Unit also executes branches.
The Integer Unit receives its operands from the Instruction Decode Unit, which is closely coupled to the Registers. These consist of 32 Integer and 32 Floating-point registers (though only the Integer registers are used in this version). The results from both arithmetic/logic and load instructions are returned to the Registers by the Write Back Unit.