Computer Architecture - Simple MIPS Model

MIPS Instructions

The instructions implemented in the model are:

Load/Store Instructions:

Instruction	Description	Example	Result
LB	Load Byte	LB R3 1(R0)	Loads Byte from memory location 1
LBU	Load Byte Unsigned	LBU R4 1(R0)	Loads Byte Unsigned from memory location 1
SB	Store Byte	SB R1 1(R0)	Stores Byte in R1 into memory location 1
LH	Load Halfword	LH R4 2(R0)	Loads Halfword from memory location 2 into R4
LHU	Load Halfword Unsigned	LHU R4 2(R0)	Loads Halfword Unsigned from memory location 2 into R4
LUI	Load Upper Immediate	LUI R1 124	Load 124 in the the upper half of regester R1
SH	Store Halfword	SH R5 6(R0)	Stores Halfword from R5 into memory loction 6
LW	Load Word	LW R4 8(R0)	Loads Word from data memory loaction word 8 into R4
SW	Store Word	SW R3 16(R0)	Stores Word in R3 into location 16 in data memory

Arithmetic Instructions:

Instruction	Description	Example	Result
ADDI	Add Immediate Word	ADDI R1 R2 -4	Store R2 + -4 in R1
ADDIU	Add Immediate Unsigned Word	ADDIU R1 R2 16	Store R2 + 16 in R1
ADD	Add Word	ADD R1 R2 R3	Store R2 + R3 in R1
ADDU	Add Word Unsigned	ADD R1 R2 R3	Store R2 + R3 in R1
SUB	Subtract Word	SUB R1 R2 R3	Store R2 - R3 in R1
SUBU	Subtract Word Unsigned	SUB R1 R2 R3	Store R2 - R3 in R1
SLT	Set on less than	SLT R1 R2 R3	If R2 is less than R3 set R1 to be 1 else set it to 0
SLTI	Set on less than Immediate	SLTI R1 R2 5	If R2 is less than 5 then set R1 to 1 else set it to 0
SLTU	Set on less than Unsigned	SLTU R1 R2 R3	If the unsigned value of R2 is less than the unsigned value R3 set R1 to 1 else set it to 0
SLTIU	Set on less than Immediate Unsigned	SLTIU R1 R2 6	If the R2 is less than 6 (after sign extension)set R1 to 1 else set it to 0

Logical Instructions:

Instruction	Description	Example	Result
AND	And	AND R1 R2 R3	Stores result of R2 AND R3 into R1
ANDI	And Immediate	ANDI R1 R1 19	Stores the result of R1 AND 19 back into R1
OR	Or	OR R1 R2 R3	Stores result of R2 OR R3 into R1
ORI	Or Immediate	ORI R1 R1 128	Stores the result of R1 OR 128 back into R1
XOR	Exclusive Or	XOR R1 R2 R3	Stores result of R2 XOR R3 into R1
XORI	Exclusive Or Immediate	XORI R1 R1 64	Stores the result of R1 OR 64 back into R1
NOR	Nor	NOR R1 R2 R3	Stores result of R2 NOR R3 into R1
SSL	Shift Word Left Logical	SSL R1 R2 4	Shift R2 4 bits to the left and store in R1
SRL	Shift Word Right Logical	SRL R1 R2 2	Shift R2 2 bits to the right and store in R1
SRA	Shift Word Right Arithmetic	SRA R3 R4 2	Arithmrticaly shift R4 2 bits right and store in R3
SLLV	Shift Word Left Logical Varable	SLLV R1 R2 R3	Shift R2 left by R3 bits and store in R1
SRLV	Shift Word Right Logical Varable	SRLV R1 R2 R3	Shift R2 right by R3 bits and store in R1
SRAV	Shift Word Right Arithmetic Varable	SRAV R1 R2 R3	Shift R2 right arithemeticaly by R3 bits and store in R1

Jump Instructions:

Instruction	Description	Example	Result
J	Jump	J 8	Jump to instruction 8
JR	Jump Register	J R1	Jump to the instruction number held in R1

Branch Instructions:

Instruction	Description	Example	Result
BEQ	Branch on equal	BEQ R1 R2 4	Branch forward 4 instructions if R1 and R2 are equal
BNE	Branch on not equal	BNE R1 R2 8	Branch forward 8 instructions if R1 and R2 are not equal
BLEZ	Branch on less than or equal to zero	BLEZ R2 -2	Branch back 2 instructions if R2 is less than or equal to zero
BGTZ	Branch on greater than zero	BGTZ R2 -2	Branch back 2 instructions if R2 is greater than zero
BLTZ	Branch on less than zero	BLTZ R2 3	Branch forward 3 instructions if R2 is less than zero
BGEZ	Branch on greater than or equal to zero	BGTZ R2 5	Branch forward 5 instructions if R2 is greater than or equal to zero
BLTZAL	Branch on less than zero and link	BLTZAL R2 3	Branch forward 3 instructions if R2 is less than zero
BGEZAL	Branch on greater than or equal to zero and link	BGTZAL R2 5	Branch forward 5 instructions if R2 is greater than or equal to zero and link

Other Instructions:

Instruction	Description	Example	Result
BREAK	Breakpoint	BREAK	Halt
NOP	No Operation	NOP	No operation