Computer Architecture Simulation & Visualisation

MIPS Processor with Scoreboard

The first scoreboard was designed as part of the CDC 6600 as a means of controlling the flow of data between registers and multiple arithmetic units in the presence of inter-instruction dependencies such as Read-After-Write. Scoreboards are still used today in a variety of modern microprocessor, though most are less complex than that used in the CDC 6600. A HASE simulation model of the MIPS-like architecture with parallel function units and a scoreboard has been built to illustrate the way scoreboards work.

The HASE MIPS/Scoreboard website explains why Scoreboards are necessary and how the HASE MIPS model works.

The files for the Simple MIPS Pipeline model are in /group/project/public-hase/Models/mips/V2.0

Instructions on how to use HASE models can be found at Downloading, Installing and Using HASE.

This MIPS model is based on an earlier model modelling the DLX architecture. The MIPS model was built by David Dolman during tenure of a University of Edinburgh College of Science & Engineering Strachan Scholarship.