EMMA-1 Processor Architecture

The Microcode Unit contains the microcode memory which is addressed by the function field of the Instruction Register in the clock cycle in which a new instruction is received from the Instruction Memory and by the Microcode Program Counter (MPC) in subsequent clock cycles. (Erroneous microcode can cause both to occur simultaneously; this is automatically detected and displayed as an error.)

EMMA operates on a two phase clock. In clock cycles in which they are active, each unit executes its internal actions in the first phase of the clock and sends out a packet result in the second phase. The Microcode Unit, for example, reads its microcode memory in the first phase and sends the appropriate microcode fields to other units, if they are active (i.e. non-zero), in the second phase.

The Program Counter and Microprogram Counter units behave identically. They contain the relevant register together with an adder which receives one of its inputs from the register itself and the other from a multiplexer (MPX) which has inputs of +1 or a value taken from BUS2 in the case of PC or the Microcode Unit in the case of MPC. Each has two outputs: Output1, which is connected to back to the adder and is permanently enabled, and Output2 which is enabled under microcode control. The microcode field controlling the Program Counter, for example, is as follows:

Whenever the PC unit is activated by receipt of a microcode packet in one clock cycle (it should also have received appropriate data packets), it activates the appropriate inputs to the multiplexer and the adder and forms the result in phase 0 of the next clock cycle; in phase 1 of that clock cycle it sends the result of the addition to Output1, back to its own Input1, (always) and to Output2 if the corresponding microcode bit is set.

The busses (BUS1 and BUS2) have a number of input connections but should receive data from only one of them in any one (phase 1) clock period. Inputs which do not receive data are set to zero. The inputs are internally ORed together (simulating a wired-OR bus) and the result is sent to all the outputs half way through the clock phase in which they were received.

The Data Memory has its own built-in Memory Address Register (MAR) and Memory Buffer Register (MBR). The microcode field controlling the memory is as follows:

For a read operation (Read/Write = 0), the address sent from BUS2 is copied into MAR in the next clock phase 0, the memory is read and the result copied into MBR. In the subsequent clock phase 1, the value in MBR is sent to BUS1. For a write operation (Read/Write = 1), the address sent from BUS2 is copied into MAR in the next clock phase 0, the data value sent from BUS1 is copied into MBR and the value is written into the memory.

The Registers unit contains 16 general purpose registers, with R0 being permanently set to 0. It receives input values from the ALU and has two outputs connected to BUS1 and BUS2. Whenever the Microcode Unit sends a microcode command to the Registers unit, it appends the appropriate source and destination register numbers extracted from the instruction in IR. In an instruction such as ADD RD RS1 RS2, the value in register RS1 is sent to BUS1 and that in RS2 to BUS2.

The ALU has two data inputs, from BUS1 and BUS2 and has two outputs, one connected to the Registers Unit and one to BUS2. Whenever the Microcode Unit sends a microcode command to the ALU, it appends the appropriate function code derived from the instruction in IR. There are two condition code bits: CC0 is set = 0 if the ALU result = 0; CC1 is set = 1 if the ALU result < 0. The ALU executes the following functions: