DASH Cluster Simulation Model
The DASH Cluster simulation model is shown on the right. The model
has a number of size and timing parameters as described below.
MIPS
The MIPS entity in the model contains an array of addresses to be sent
to the Primary Cache. At the start of the simulation, the MIPS sends
the first of these addresses, together with its Read/Write type, to
the Primary Cache. Once the actions in the cache system are complete
and the MIPS has received a reply, it sends the next address, and so
on until it encounters an address of type z.
Primary Cache
The primary cache is direct-mapped and operates a
write-through/no-write-allocate policy. The line size is fixed at 4
words but the number of lines can be varied from 1 to 256 in multiples
of 2 while the delay associated with a cache access can be varied from
1 to 8 clock cycles. As it processes each access, the cache icon
displays the result (RH = Read Hit, RM = Read Miss, WH = Write Hit, WM
= Write Miss).
The data structure central to the operation of this entity is a HASE
memory array which represents the cache memory contents via a C++
based array of structs. This structure specifies storage for valid,
modified and shared bits as well as the cache entry tag and stored
values:
Valid Modified Shared Tag Block A0 A1 A2 A3
- Valid (1 = valid, 0 = invalid)
- Modified = 1 indicates that the line has been the target of a write
but note that this never gets set to 1 in the Primary Cache);
0 = Unmodified
- Shared = 1 indicates that there is a copy of the line in another
cache;
Shared = 0 indicates exclusive ownership
- Tag = memory address of cache line
- Block (= address/4) is part of the display, but not part of the model
- A0 A1 A2 A3 are the addresses of the 4 words in the line
This cache line format is shared with the secondary cache unit; the
only difference in use is that the primary cache need never use the
shared bit. On receipt of an incoming packet a table lookup is
performed and validity bit and tag checks are made. If a hit occurs a
delay is initiated before sending the result back to the MIPS entity.
On a miss the packet is referred (after the miss delay) to the
secondary cache entity.
Secondary Cache
The secondary level processor cache is identical to the primary cache
except that it operates a write-back/write-allocate policy. As in the
Primary Cache, the user can define cache size and latency through the
use of entity parameters.
A line in the Secondary Cache may be:
- Invalid
- Exclusive-Unmodified (EU)
- Shared-Unmodified (SU)
- Exclusive-Modified (EM)
The MPBus
In the full model of a cluster the MPBus (q.v.) is one of the
most complex entities in the simulation. It is responsible for
displaying a large amount of state information detailing the on-going
operation of the snoopy-bus protocol as well as carrying out the
conventional tasks of bus arbitration, address and data transfer.
The Cluster Memory
The cluster memory is relatively simple in design. Because the
simulation is only concerned with modelling the effects of read/writes
throughout the system (and not the contents of memory locations) no
actual storage needs to be modelled other than that present in the
processor caches (and in these only addresses need be stored).
Therefore a memory unit cycle consists of receiving an
in-bound request, displaying read/write information on-screen and
finally transmitting the result packet back onto the MPbus.
Parameters
The model has a number of size and timing parameters which can be
varied.
The parameters are:
| Parameter | Nominal Value |
| MIPS_delay | 1 |
| P_cache_delay | 1 |
| P_cache_size (256 max) | 8 |
| S_cache_delay | 2 |
| S_cache_size (1024 max) | 16 |
| M_size | 4096 |
| M_delay | 4 |
| Bus_arb_delay | 1 |
| Bus_add_delay | 3 |
| Bus_data_delay | 4 |
The maximum number of cycles which the model executes can also be
varied. This parameter is included so that if the termination access
type is missing from one of the processor input files, the simulation
will not run for ever.
HASE Project
Institute for Computing Systems Architecture,
School of Informatics, University of Edinburgh
Last change 22/11/2005