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Institute for Computing Systems Architecture

Computer Architecture Simulation & Visualisation

The Cray-1

The Cray-1 model and these webpages are likely to be further developed

The Cray-1 was the logical successor to the CDC 7600. The instruction issue bottleneck in the 7600 which prevented floating-point operations from being executed at a rate in excess of 1 per clock was overcome in the CRAY-1 processor by the use of vector orders, which caused streams of up to 64 data elements to be processed as a result of one instruction issue. Vectors were contained in a set of eight V registers, each capable of holding 64 elements (each of 64 bits), and a typical vector instruction caused sets of operands to be taken from two V registers and the results to be returned to a third.

The HASE Cray-1 website describes the design of the Cray-1 central processor and explains how the HASE simulation model works. There are three demonstration programs that can be run on the model. These are contained in files Program1.txt, Program2.txt and Program3.txt in the Programs subdirectory included with the model files. To change programs, the appropriate program file should be copied into PROGRAM.prog_mem.mem and the model re-loaded into HASE. When downloaded, PROGRAM.prog_mem.mem contains Program1.

The model files be downloaded from cray1_v1.2.zip.

This Cray 1 model was originally built as an MSc project by Helen Berringer in 1998. It has since been considerably revised by Roland Ibbett.

Instructions on how to use HASE models can be found at Downloading, Installing and Using HASE.

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HASE Project
Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh
Last change 23/01/2019