The memory simply contains data values. The processors are modelled as arrays containing sequences of read and write requests to locations in the memory address space, e.g.
| R | 0 | 0 |
| R | 9 | 0 |
| W | 1 | 475 |
| W | 1 | 541 |
| Z | 0 | 0 |
Both write and read requests require a data field, because of the way the processor is modelled. At the start of the simulation, each processor sends its first request to its cache and, when it receives a response, issues the next request in the succeeding clock period. When it encounters a request which is not r, R, w or W, this is treated as an end-of-list marker and the processor then increments a global nodes_done variable. nodes_done is monitored by the bus in each clock period and when it reaches 4, the bus stops the simulation. If the user omits an end-of-list marker, the simulation will eventually be stopped by a time-out.
The caches each contain 8 lines, each of which contains the following fields:
| Valid | Address | Data |
The caches send and receive packets to/from their respective processors and to/from the bus. The actions that occur in response to a processor request depend on whether it is a read or write request and whether the request gets a hit or a miss in the cache. Except in in the case of a read hit, the cache sends a packet to the bus, destined for the memory. Bus packets contain the following fields:
| Packet Type | MR | Memory Read Request | |
| MW | Memory Write Request | ||
| MA | Memory Acknowledge | ||
| Address | |||
| Data | |||
| Source | Number of the originating cache | ||
| Outcome | State | Action |
| Read Hit | RH | Send data to processor |
| Read Miss | RM |
1. Issue Memory Read (MR) 2. When memory replies (MA), write data to cache and send to processor |
| Outcome | State | Action |
| Write Hit | WH | 1. Send MW packet to memory 2. When memory replies (MA), write data to cache, send ack to processor |
| Write Miss | WM | 1. Send MW packet to memory 2. When memory replies (MA), write data to cache, send ack to processor |
For both RM and WM, the required line in the cache can simply be overwritten with the new address and data because even if the line already contains a valid entry, the data value in memory is guaranteed to be the same as that in the cache: new values created by write requests are always written to the memory as well as to the cache. Similarly, because this is a Write Through protocol, the actions for WH and WM are virtually identical.
For a Write Hit or Write Miss, the cache is updated only after the cache has received an MA packet. This is because, in a real implementation, each cache line would contain typically four words, rather than the one word in this model, and write requests only affect one word at time. So the line written into the cache would contain three of the four values sent from memory (as part of the MA response) and one sent from the processor.
Any packet sent to the bus is forwarded to all the caches and the memory. The memory only responds to packets sent to it; a packet sent from the memory contains the same source address as the packet it received. The caches act on MA packets containing their own source number and to MW packets sent by other caches. If an MW packet sent by a different cache contains the same address as a valid address in one of its own lines, it sets the Valid bit for that line to 0. If the cache has an outstanding read or write request when it invalidates a line (i.e. it is waiting for a turn to access the bus), it re-checks for a Hit or Miss.
Note that the model does not contain a mechanism to ensure exclusive access to data values. In a real multiprocessor system such a mechanism would exist, to avoid two processors attempting to update the same variable simultaneously and thus (at least potentially) leading to software malfunctioning.