COMPENTITY - A Higher Level Architecture Entity

Syntax

COMPENTITY entity_type_name (

DESCENDANTS ( descendant, ... )
DESCRIPTION ("description")
PARAMS ( reference_parameter, ... )
PORTS ( port, ... )

)

Synopsis

The COMPENTITY declaration enables the creation of higher level architecture components. This is used to group entities and/or other higher level entities together along with their interconnections into one entity, allowing the operation of the lower level components to be abstracted out.

descendants - The descendant components describe which entities and their interconnections are to be used to compose the higher level. Therefore the descendant_component can be of two types, a child entity or a link
entity_type_name str - The name of the type of higher level entity to be created. This is used to create instances of the component in the architecture, and to identify the correct simulation code and icon.
description str - A description of an aspect of the higher level entity.
reference_parameter - This section of the higher level entity defintion describes the parameters that are associated with it. For example, a memory entity may have an array associated with it to hold the contents, and an integer to hold the access time of the component. Careful selection of the parameters could result in reusable components. For example a cache entity might have parameters for its size, associativity and access time. See the reference section.
port - This section of the entity definition describes the ports of the entity. The ports are the entities' means of communicating with the other entities. Ports of different entities are connected together to form a communication channel. If there are any unconnected ports on the lower level entities these are inherited by the higher level entity. These two ports then behave as one, so if the higher level port is then linked to a different component, the lower level port is automatically connected too. This inheritance can be performed at multiple levels.

Example

COMPENTITY Computer (

DESCENDANTS (

CHILD ( Mem, main_mem )
CHILD ( CPU, processor )
CLINK ( CPU.processor[to_mem]->Mem.main_mem[from_proc], 3)

)
DESCRIPTION ( "A basic computer" )
PARAMS (

RARRAY ( Memory, cache_contents )
RINT ( access_time, 2 )
RENUM ( Associativity, cache_assoc, 0 )

)
PORTS (

PORT ( to_cpu, LinkData, SOURCE )
PORT ( from_cpu, LinkData, DESTINATION )
PORT ( to_main_mem, LinkData, SOURCE )
PORT ( from_main_mem, LinkData, DESTINATION )

)



PROJECT(

	    
	    
	    PREAMBLE(
			 
			 NAME "project_name"

			 DIRECTORY "working_directory"

			 AUTHOR "project_author"

			 VERSION ver

			 DESCRIPTION "project_description"

			 
			 COMPILER "compiler_name"

			 LINK "linker_name"

			 LIBRARY "library_options"

			 EXTERN lib1, ...
			       
			 )

      PARAMLIB(parameter, ...)

      GLOBALS(reference_parameter, ...)

      ENTITYLIB(
         entity_definition | higher_entity_definition | 
         mesh_entity | abstract_entity, ...)

      STRUCTURE(architecture_entity | communication_channel , ... )
   
)

Home : Research : Groups : Hase : Manuals : Edl

Please contact our webadmin with any comments or changes.
Unless explicitly stated otherwise, all material is copyright © The University of Edinburgh.