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Institute for Computing Systems Architecture

Ph.D. Project Opportunities

This page gives information about some Ph.D. project topics currently proposed by potential supervisors in ICSA.

Projects in Self-Timed Systems Design and Testing, Computer Micro-architecture

Supervisor:Aris Efthymiou

I am interested in the interface between circuit design and computer architecture with a focus on self-timed or asynchronous circuits and systems. A sample of research topics suitable for PhD research in these areas.

For more detailed descriptions, please read this page and scroll down the list to find the above headings.

Projects in Skeletal Parallel Programming

Supervisor: Murray Cole

The skeletal approach to parallel programming advocates the use of program forming constructs which abstract commonly occuring patterns of parallel computation. In effect, these constructs define a co-ordination language into which fragments of lower level (either sequential or explicitly parallel) code can be inserted. There is a range of opportunities for developments in this area:

Projects in Optimisation and Compilation

Supervisor: Michael O'Boyle

The primary research question I am interested in is: how can compiler technology best exploit the potential of high performance architectures? This work involves developing new theory and optimisation techniques and then prototyping these ideas in experimental compilers. Compilers are one component in high performance computing and I am interested in their interaction with other components, most notably architecture design. My research interests include:

  • Adaptive compilation. Compilers are unable to keep up with the sustained evolution of computer architecture. Novel techniques are therefore needed which allow the compiler to learn about the underlying architecture by exploring a transformation based optimisation space.
  • Auto-parallelising compilers. How can compiler analysis and program transformation automatically map a sequential program into an efficient parallel form?
  • Optimising for memory hierarchy. Memory latency is the primary bottleneck in processor performance. How can static and dynamic analysis be synthesised to suggest appropriate transformations to improve memory hierarchy utilisation?
  • Linear program transformation theory and practice. Program transformation is very ad hoc and real barrier to systematic program optimisation. New unifying approaches are therefore needed.
  • Compiler directed memory coherence. Hardware based schemes may be expensive and reactive rather than pro-active. Can compiler technology improve on this?
  • Java Grande. I am interested in how we can use existing and novel techniques to improve the performance of Java programs.
  • Very High level programming languages. I am interested in how languages such as ALDOR, which provide great expressive power may be implemented on high performance computers, especially with regard to QCD applications.
  • I am also interested in Compiler impact on architecture and the Parallelisation of commercial languages and applications.

  • Projects in Computer Architecture

    Supervisor: Marcelo Cintra

    I am interested in supervising research in any topic related to computer architecture design. In particular, my main research topics currently are:

    Projects in Computer Architecture

    Supervisor: Nigel Topham

    There is a strong synergy between computer architecture and compilers - many architectural innovations rely upon increasingly sophisticated optimizations, whereas optimizations such as auto-parallelization and code generation for instruction-level parallelism typically rely upon certain underlying hardware structures. The research topics below address the general question of how to exploit higher levels of integration in the quest for increasing performance in future computing systems, particularly embedded systems.

    Projects in Software Tools for Embedded Systems

    Supervisor: Bjoern Franke

    Only about 2% of all microprocessors made drive PCs, the other 98% is embedded CPUs. However, unlike the PC domain there is no single processor architecture dominating the embedded domain. In fact, there is a large number of sometimes highly specialised processors for widely varying applications. Idiosyncratic architectures, specialised applications and the demand low cost, high performance solutions often operating under real-time constraints challenge traditional software tools, making it necessary to investigate new approaches in the area of tool support for embedded systems.

    My main research interests are currently:

  • HW/SW Co-Design Space Exploration for Application-Specific Processors. Certain embedded applications justify the development of an application-specific instruction set processor. Trading off partially contractory goals such as optimisation for high performance, low power, low cost, easy programmibility etc. and efficiently searching a huge and complex optimisation space are major challenges in the design of such systems.
  • Code Generation for Configurable Processors Configurable processors are flexible yet application specific IP cores and allow customisation and extension of a generic architecture template for a new application domain. While this approach to hardware customisation is flexible, it can produce complex instruction patterns challenging current compiler technology.
  • Parallelisation and Code Optimisation for Network Processors Network processors are application specific devices optimised to support network protocols at the highest possible speed. Their adaptation has a strong impact on the programmability of these devices and makes software development a time-consuming and expensive task.

  • Projects in Networking

    Supervisor: Mahesh Marina

    My current research is mainly in the area of wireless and mobile networking, focusing on issues such as performance, reliability, self-configuration and heterogeneity. Sample topics include:

  • Dynamic spectrum access and cognitive radios
  • Cross-layer and coding techniques for reliable and efficient wireless networking
  • Low-cost, robus networking and applications for developing regions
  • Peformance enhancement techniques for wireless mesh networks
  • Enabling robust Internet access in vehicular access networks
  • Self-configuration algorithms for hybrid wireless networks
  • Protocols for RFID networks
  • Testbeds and measurement frameworks for multihop wireless networks
  •   Brief descriptions for some of these topics are accessible via the School of Informatics website on research topics for prospective PhD students.

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