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Test generation for asynchronous circuit design is currently a promising topic to endeavour. Logic synthesis and simulation of asynchronous circuit compared to its synchronous counterpart is considered to be complex and tedious, due to the lack of global clock. Given that, test generation for such a class of circuits poses tremendous challenge over the generation of optimal algorithms to generate test vectors. Controllability of the circuits is reduced due to the absence of the clock and this makes the test generation difficult. Full scan design based test generation seems to be promising in terms of controllability and test generation, but at the cost of the hardware. To trade -off the area overhead, partial scan design was introduced which considerably reduced the extra logic required to make the design testable. This work focuses on automating the process of test generation based on this partial scan design. Several different methods and approaches to generate test patterns for asynchronous circuits are experimented.
