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The success of the design of Systems on Chip and other embedded systems, is highly sensitive to technical constraints such as performance, power dissipation and die area, as well as non-technical constraints such as time-to-market and the cost of verification and design effort. High-level synthesis systems, which transform behavioural system descriptions to RTL-level specifications, have the potential to reduce time-to-market and design effort cost, but have not seen widespread commercial use due to poor performance, and are not a good fit with modern SoCs.
An iterative microarchitecture synthesis system is proposed, targeting the synthesis of ISP microarchitectures, and extension logic for existing customisable ISPs, which will use iterative techniques to more effectively evaluate and hence improve the effectiveness of its results, while providing a better fit with modern SoC design methodologies. This will be used to establish the relative effectiveness of iterative high-level synthesis methods compared to methods used by existing systems, and provide a framework for further research.
