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The fixed control hardware, instruction set processor architecture of conventional microprocessors sacrifices absolute performance for generic programmability. In contrast reconfigurable FPGA technology allows the implementation of specialised high performance applications, but at the expense of programming complexity. We seek to address the challenge of providing programming models which can target systems combining conventional and reconfigurable technology as appropriate. This involves the design of new abstraction techniques. A common approach to general-purpose parallel computation is based on packaging complex operations as templates, patterns or skeletons, which encapsulate the necessary control and data flow. This allows software to be written in a way that is independent of particular architectures and hence portable. Our research is guided toward the use of algorithmic skeletons in the FPGA design process. These can be provided though sequential programming interfaces to parallel (and dynamically reconfigured) skeletons and used as a tool for exploring FPGA/microprocessor design spaces.
