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Field programmable logic (FPL), such as the Field Programmable Gate Array (FPGA), can be configured post-manufacture to adapt its hardware resources to the particular algorithm to be implemented. It has emerged as the third computing fabric alternative alongside the processor and custom logic for the increasingly complex and expensive job of the chip architect. The enhanced density and functionality made possible by reconfiguring FPL at run-time, or "dynamically", has been the subject of much excitement and research in this area. This talk will present the results of recent work on a new approach to rapid dynamic reconfiguration of an FPGA.
