The Stanford DASH architecture was designed to prove the feasibility of building a scaleable high performance machine with multiple coherent caches and a single address space. There are currently two HASE simulation models of parts of the DASH architecture, one modelling a single node and one modelling a cluster of four nodes. These models are designed to demonstrate the cache coherency protocols used in the DASH. The Node model demonstrates a simple 2-level cache arrangement.Return to HASE home page
The HASE DASH Node Architecture Website describes the DASH architecture and explains how the HASE Node model works.
The JavaHASE simulation applet for the DASH Node can be accessed from the HASE Scoreboards Website or can be downloaded directly: