Program (List of Talks): WEDNESDAY 9.00 - 9.40 Registration 9.40 - 9.45 Welcome Instruction Level Parallelism 9.45 - 10.10 Experiments with Automatic Vectorization for the Pentium (r) 4 Processor A.Bik, M. Girkar, P. Grey, and X. Tian 10.10 - 10.35 Schedule Independent Register Allocation for Software Pipelining Sid Ahmed Ali Touati and Christine Eisenbeis, INRIA, Rocquencourt 10.35 - 11.00 URACAM: A Unified Register Allocation, Cluster Assignment and Modulo Scheduling Approach Josep M. Codina, Jesus Sanchez and Antonio Gonzalez 11.00 - 11.30 COFFEE BREAK Feedback Directed Compilation 11.30 - 11.55 The Effect of Cache Models on Iterative Compilation for Combined Tiling and Unrolling T. Kisuki and P.M.W. Knijnenburg and K. Gallivan and M.F.P. O'Boyle 11.55 - 12.20 Towards Retargetable Compilers --- Feedback Directed Compilation Using Genetic Algorithms Andy Nisbet 12.20 - 12.45 Searching for the Best FFT Formulas with the SPL Compiler J. Johnson (Drexel), R. Johnson (MathStar Inc), D. Padua (UIUC) and J. Xiong (UIUC) 12.45 - 2.45 LUNCH BREAK Distributed Computing 2.45 - 3.10 Parallel Object-Oriented Framework Optimization Dan Quinlan 3.10 - 3.35 Exploiting Object Locality in JavaParty, a Distributed Computing Environment for Workstation Clusters Bernhard Haumacher and Michael Philippsen 3.35 - 4.00 Compiler and Middleware Support for Scalable Data Mining Gagan Agrawal 4.00 - 4.30 COFFEE BREAK Linear Algebraic Approaches 4.30 - 4.55 On Code-Generation in the Polyhedral Model Fabien Quilleré & Sanjay Rajopadhye, IRISA, Rennes, France 4.55 - 5.20 The Minimal Number of Communication Startups when Tiling Space-Time Mapped Programs Martin Griebl 5.20 - 5.45 Minimizing Strides in Loops with Affine Array References Ph. Clauss, V. Loechner, B. Meister, ICPS/LSIIT, Universite Louis Pasteur, Strasbourg, France THURSDAY Program Analysis 9.00 - 9.25 Dependence Testing Without Induction Variable Substitution Albert Cohen (INRIA Rocquencourt), Peng Wu (DCS, University of Illinois) 9.25 - 9.50 Demand-Driven Data-Flow Analysis of Explicitly Parallel Programs: An Approach Based on Reverse Data-Flow Analysis Jens Knoop 9.50 - 10.15 Fast and Accurate Evaluation of Memory Performance Upper-Bound Grigori Fursin, Mike O'Boyle, Olivier Temam and Gregory Watts 10.15 - 10.45 COFFEE BREAK Managing Paralleism 10.45 - 11.10 Automatic Coarse Grain Task Parallel Processing Using OSCAR Multigrain Parallelizing Compiler Motoki Obata, Kazuhisa Ishizaka, Hironori Kasahara, Waseda University 11.10 - 11.35 Orthogonal Processor Groups for Message-Passing Programs Thomas Rauber, Robert Reilein, Gudula Runger 11.35 - 12.00 Managing irregular remote accesses to distributed shared arrays in a bulk-synchronous parallel programming environment Christoph Kessler 12.00 - 12.25 Clustering and Scheduling of simulation code from equation based simulation languages Peter Aronsson and Peter Fritzson, PELAB, Dept. of Computer and Information science, Linköpings Universistet Sweden 12.25 - 2.25 LUNCH BREAK Parallelism and Memory 2.25 - 2.50 A Compiler for Multiple Memory Models Sam Midkiff, Jaejin Lee, David Padua 2.50 - 3.15 The Gilgamesh Processor-in-Memory Architecture and Its Execution Model Hans Zima and Thomas Sterling 3.15 - 3.40 Compiler and Language Issues for the Blue Gene Massively Parallel Systems Jose E. Moreira, Sam P. Midkiff, and Manish Gupta; IBM Thomas J. Watson Research Center 3.40 - 4.10 COFFEE BREAK Parallelisation 4.10 - 4.35 Compiling Data Parallel Programs for Clusters of SMPs Siegfried Benkner, ISS, University of Vienna, Austria and Thomas Brandes, SCAI.WR, GMD, Germany 4.35 - 5.00 A compiler framework for rule-based parallelisation F. Kuijlman, W.J.A. Denissen, C. van Reeuwijk, H.J. Sips 5.00 - 5.25 On Efficient Parallelization of Line-Sweep Computations Alain Darte, Daniel Chavarria-Miranda, Robert Fowler, John Mellor-Crummey Rice University, Houston, TX USA and LIP, ENS-Lyon, France FRIDAY Embedded and Multimedia Systems 9.00 - 9.25 Address Register-Oriented Optimizations for Embedded Processors J. Ramanujam, J. Hong, M. Kandemir and S. Atri Louisiana State Universuty and The Pennsylvania State University 9.25 - 9.50 A Retargetable Preprocessor for Multimedia Instructions Giles Pokam, Julien Simonnet and Francois Bodin 9.50 - 10.15 Energy-Conscious Instruction Scheduling for VLIW Architectures A. Parikh, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and I. Kadayif 10.15 - 10.45 COFFEE BREAK Java 10.45 - 11.10 A Framework for Efficient Reuse of Binary Code in Java Pramod G. Joisha, Samuel P. Midkiff, Mauricio J. Serrano, Manish Gupta 11.10 - 11.35 Compile Time Elimination of Null- and Bounds-Checks Jeffery von Ronne, Michael Franz, Niall Dalton, Wolfram Amme 11.35 - 12.00 Java Compilation for Multi-threaded Architectures D.K.Arvind, J. Hossell, A. Kopp, R. Rangaswami 12.00 - 2.00 LUNCH BREAK Performance Modelling and Prediction 2.00- 2.25 Static Performance Estimation of Data-Dependent Parallel Programs Hasyim Gautama, Arjan J.C. van Gemund, Delft University of Technology, The Netherlands 2.25 - 2.50 Compiler Support for Parallel Program Performance Prediction Rizos Sakellariou and Vikram Adve 2.50 - 3.15 Predicting the Impact of Implementation Level Aspects on Parallel Application Performance Arturo González-Escribano, Arjan J.C. van Gemund, Valentín Cardeñoso-Payo 3.15 - 3.45 COFFEE BREAK Array Optimisation 3.45 - 4.10 A Case for Array Merging in Memory Hierarchies Daniela Genius and Sylvain Lelait 4.10 - 4.35 Plurality: a new and useful concept in Automated Parallelisation J M MacLaren 4.35 - 5.00 Partial Array Expansion for Irregular Reductions Eladio Gutierrez, Oscar Plata and Emilio L. Zapata